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ds05-20887-1e fujitsu semiconductor data sheet flash memory cmos 64 m (8 m 8/4 m 16) bit dual operation mbm29dl640e 80/90/12 n n n n description the mbm29dl640e is a 64 m-bit, 3.0 v-only flash memory organized as 8 mbytes of 8 bits each or 4 mwords of 16 bits each. the device is offered in 48-pin tsop (i) and 63-ball fbga packages. this device is designed to be programmed in system with 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the device is organized into four physical banks: bank a, bank b, bank c and bank d, which can be considered to be four separate memory arrays as far as certain operations are concerned. this device is the same as fujitsus standard 3 v only flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simulta- neously taking place on the other bank. (continued) n n n n product line up n n n n packages part no. mbm29dl640e ordering part no. v cc = 3.3 v 80 ?? v cc = 3.0 v ? 90 12 max. address access time (ns) 80 90 120 max. ce access time (ns) 80 90 120 max. oe access time (ns) 30 35 50 + 0.3 v - 0.3 v + 0.6 v - 0.3 v 48-pin plastic tsop (i) 48-pin plastic tsop (i) 63-ball plastic fbga (fpt-48p-m19) (fpt-48p-m20) (bga-63p-m02) marking side marking side
mbm29dl640e 80/90/12 2 (continued) in the device, a new design concept called flexbank tm * 1 architecture is implemented. using this concept the device can execute simultaneous operation between bank 1, a bank chosen from among the four banks, and bank 2, a bank consisting of the three remaining banks. this means that any bank can be chosen as bank 1. (refer to functional description for simultaneous operation.) the standard device offers access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed microprocessors without the wait. to eliminate bus contention the device has separate chip enable (ce ) , write enable (we ) and output enable (oe ) controls. this device consists of pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program algorithm tm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm tm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies the proper cell margin. a sector is typically erased and verified in 1.0 second (if already completely preprogrammed) . the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once a program or erase cycle has been completed, the device internally resets to the read mode. the device also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore if a system reset occurs during the embedded program tm * 2 algorithm or embedded erase tm * 2 algorithm, the device is automatically reset to the read mode and have erroneous data stored in the address locations being programmed or erased. these locations need rewriting after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the device memory electrically erases the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection. *1: flexbank tm is a trademark of fujitsu limited. *2: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29dl640e 80/90/12 3 n n n n features ? 0.23 m m process technology ? simultaneous read/write operations (dual bank) ? flexbank tm bank a : 8 mbit (8 kb 8 and 64 kb 15) bank b : 24 mbit (64 kb 48) bank c : 24 mbit (64 kb 48) bank d : 8 mbit (8 kb 8 and 64 kb 15) two virtual banks are chosen from the combination of four physical banks (refer to table 9, 10) host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. read-while-erase read-while-program ? single 3.0 v read, program, and erase minimized system level power requirements ? compatible with jedec-standard commands uses the same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 48-pin tsop (i) (package suffix : tn - normal bend type, tr - reversed bend type) 63-ball fbga (package suffix : pbt) ? minimum 100,000 program/erase cycles ? high performance 80 ns maximum access time ? sector erase architecture sixteen 4 kword and one hundred twenty-six 32 kword sectors in word mode sixteen 8 kbyte and one hundred twenty-six 64 kbyte sectors in byte mode any combination of sectors can be concurrently erased. it also supports full chip erase. ? hidden rom (hi-rom) region 256 byte of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of outermost 2 8 kbytes on both ends of boot sectors, regardless of sector protection/ unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance ? embedded erase tm algorithms automatically preprograms and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address (continued)
mbm29dl640e 80/90/12 4 (continued) ? data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, the device automatically switches itself to low power mode. ? low v cc write inhibit 2.5 v ? program suspend/resume suspends the program operation to allow a read in another byte ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector group protection hardware method disables any combination of sector groups from program or erase operations ? sector group protection set function by extended sector group protection command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin. ? in accordance with cfi (c ommon f lash memory i nterface)
mbm29dl640e 80/90/12 5 n n n n pin assignments (continued) tsop (i) (fpt-48p-m19) (fpt-48p-m20) a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 we reset a 21 wp/acc ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 standard pinout a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 (marking side) reverse pinout a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by wp/acc a 21 reset we a 20 a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 (marking side)
mbm29dl640e 80/90/12 6 (continued) fbga (top view) (bga-63p-m02) a8 b8 l8 m8 n.c. n.c. n.c. n.c. a7 b7 c7 d7 e7 f7 g7 h7 j7 k7 l7 m7 n.c. n.c. a 13 a 12 a 14 a 15 a 16 bytedq 15 /a -1 v ss n.c. n.c. c6 d6 e6 f6 g6 h6 j6 k6 a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 c5 d5 e5 f5 g5 h5 j5 k5 we reset a 21 a 19 dq 5 dq 12 v cc dq 4 c4 d4 e4 f4 g4 h4 j4 k4 ry/by wp/acc a 18 a 20 dq 2 dq 10 dq 11 dq 3 c3 d3 e3 f3 g3 h3 j3 k3 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 a2 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 n.c. a 3 a 4 a 2 a 1 a 0 ce oe v ss n.c. n.c. a1 b1 l1 m1 n.c. n.c. n.c. n.c. (marking side)
mbm29dl640e 80/90/12 7 n n n n pin descriptions table 1 mbm29dl640e pin configuration pin function a 21 to a 0 , a -1 address input dq 15 to dq 0 data input/output ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector group unprotection byte selects 8-bit or 16-bit mode wp /acc hardware write protection/program acceleration v ss device ground v cc device power supply n.c. no internal connection
mbm29dl640e 80/90/12 8 n n n n block diagram n n n n logic symbol v cc v ss a 21 to a 0 (a -1 ) reset we ce oe byte wp/acc dq 15 to dq 0 dq 15 to dq 0 bank a address bank c address bank b address bank d address state control & command register status ry/by control cell matrix 8 mbit (bank a) x-decoder y-gating cell matrix 8 mbit (bank d) x-decoder y-gating cell matrix 24 mbit (bank b) x-decoder y-gating cell matrix 24 mbit (bank c) x-decoder y-gating 22 a 21 to a 0 we oe ce dq 0 to dq 15 16 or 8 byte reset a -1 ry/by
mbm29dl640e 80/90/12 9 n n n n device bus operation table 2 mbm29dl640e user bus operations (byte = v ih ) legend : l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. seetable 4. *2: refer to section on sector group protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.3 v 10 % *5: it is also used for the extended sector group protection. *6: protect outermost 2 8 kbytes (4 kwords) on both ends of the boot block sectors. (continued) operation ce oe we a 0 a 1 a 2 a 3 a 6 a 9 dq 15 to dq 0 reset wp / acc auto-select manufacturer code * 1 llhlllllv id code h x auto-select device code * 1 llhhllllv id code h x extended auto-select device code * 1 l lhlhhhlv id code h x l lhhhhhlv id code h x read * 3 llha 0 a 1 a 2 a 3 a 6 a 9 d out hx standby h x xxxxxxx high-z h x output disable lhhxxxxxx high-z h x write (program/erase) l h l a 0 a 1 a 2 a 3 a 6 a 9 d in hx enable sector group protection * 2, * 4 lv id lhlllv id xhx verify sector group protection * 2, * 4 llhlhlllv id code h x temporary sector group unprotection * 5 xxxxxxxxx x v id x reset (hardware) /standby x x xxxxxxx high-z l x boot block sector write protection * 6 xxxxxxxxx x x l
mbm29dl640e 80/90/12 10 (continued) table 3 mbm29dl640e user bus operations (byte = v il ) legend : l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see table 4. *2: refer to section on sector group protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc = 3.3 v 10 % *5: also used for extended sector group protection. *6: protects outermost 2 8 kbytes (4 kwords) on both ends of the boot block sectors. operation ce oe we dq 15 /a -1 a 0 a 1 a 2 a 3 a 6 a 9 dq 7 to dq 0 reset wp / acc auto-select manufacturer code * 1 llh l lllllv id code h x auto-select device code * 1 llh l hllllv id code h x extended auto-select device code * 1 l lh l lhhhlv id code h x l lh l hhhhlv id code h x read * 3 llha -1 a 0 a 1 a 2 a 3 a 6 a 9 d out hx standby h x x x xxxxxx high-z h x output disable lhh x xxxxxx high-z h x write (program/erase) l h l a -1 a 0 a 1 a 2 a 3 a 6 a 9 d in hx enable sector group protection * 2, * 4 lv id l lhlllv id xhx verify sector group protection * 2, * 4 llh l lhlllv id code h x temporary sector group unprotection * 5 xxx x xxxxxx x v id x reset (hardware) / standby xxx x xxxxxx high-z l x boot block sector write protection * 6 xxx x xxxxxx x x l
mbm29dl640e 80/90/12 11 table 4 mbm29dl640e command definitions (continued) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/ reset word 1xxxhf0h byte read/ reset word 3 555h aah 2aah 55h 555h f0h ra rd byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0h pa pd byte aaah 555h aaah program suspend 1 bab0h program resume1 ba30h chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 bab0h erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program * 1 word 2 xxxh a0hpapd byte xxxh reset from fast mode * 1 word 2 ba 90h xxxh * 4 f0h byte ba xxxh extended sector group protection * 2 word 4 xxxh 60h spa 60h spa 40h spa sd byte query word 1 (ba) 55h 98h byte (ba) aah
mbm29dl640e 80/90/12 12 (continued) *1: this command is valid during fast mode. *2: this command is valid while reset = v id . *3: this command is valid during hi-rom mode. *4: the data 00h is also acceptable. notes : 1. address bits a 21 to a 11 = x = h or l for all address commands except or program address (pa) , sector address (sa) , bank address (ba) and sector group address (spa) . 2. bus operations are defined in tables 2 and 3. 3. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 will uniquely select any sector. ba = bank address. address setted by a 21 , a 20 , a 19 will select bank a, bank b, bank c and bank d. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5. spa = sector group address to be protected. set sector group address and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) . sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6. hra = address of the hi-rom area word mode : 000000h to 00007fh byte mode : 000000h to 0000ffh 7. hrba = bank address of the hi-rom area (a 21 = a 20 = a 19 = v il ) 8. the system should generate the following address patterns: word mode : 555h or 2aah to addresses a 10 to a 0 byte mode : aaah or 555h to addresses a 10 to a 0 , and a -1 9. both read/reset commands are functionally equivalent, resetting the device to the read mode. command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data hi-rom entry word 3 555h aah 2aah 55h 555h 88h byte aaah 555h aaah hi-rom program * 3 word 4 555h aah 2aah 55h 555h a0h (hra) pa pd byte aaah 555h aaah hi-rom exit * 3 word 4 555h aah 2aah 55h (hrba) 555h 90hxxxh00h byte aaah 555h (hrba) aaah
mbm29dl640e 80/90/12 13 table 5.1 mbm29dl640e sector group protection verify autoselect codes *1 : a -1 is for byte mode. *2 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it becomes possible to activate simultaneous operation. *4 : at word mode, a read cycle at address (ba) 01h (at byte mode, (ba) 02h) outputs device code. when 227eh (at byte mode, 7eh) is output, it indicates that two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh (at byte mode, (ba) 1ch) , as well as at (ba) 0fh (at byte mode, (ba) 1eh) . table 5.2 expanded autoselect code table (b) : byte mode (w) : word mode type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 a -1 *1 code (hex) manufactures code ba *3 v il v il v il v il v il v il 04h device code byte ba *3 v il v il v il v il v ih v il 7eh word x 227eh extended device code *4 byte ba *3 v il v ih v ih v ih v il v il 02h word x 2202h byte ba *3 v il v ih v ih v ih v ih v il 01h word x 2201h sector group protection sector group addresses v il v il v il v ih v il v il 01h *2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 / 0 000000000000100 device code (b) 7eh a -1 hi- z hi- z hi- z hi- z hi- z hi- z hi- z 01111110 (w) 227eh 0010001001111110 extended device code (b) 02h a -1 hi- z hi- z hi- z hi- z hi- z hi- z hi- z 00000010 (w) 2202h 0010001000000010 (b) 01h a -1 hi- z hi- z hi- z hi- z hi- z hi- z hi- z 00000001 (w) 2201h 0010001000000001 sector group protection 01h a -1 / 0 000000000000001
mbm29dl640e 80/90/12 14 n n n n flexible sector-erase architecture table 6.1 sector address tables (bank a) note : the address range is a 21 : a -1 if in byte mode (byte = v il ) . the address range is a 21 : a 0 if in word mode (byte = v ih ) . bank sec- tor sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0000000000 8/4 000000h to 001fffh 000000h to 000fffh sa1 0000000001 8/4 002000h to 003fffh 001000h to 001fffh sa2 0000000010 8/4 004000h to 005fffh 002000h to 002fffh sa3 0000000011 8/4 006000h to 007fffh 003000h to 003fffh sa4 0000000100 8/4 008000h to 009fffh 004000h to 004fffh sa5 0000000101 8/4 00a0 00h to 00bfffh 005000h to 005fffh sa6 0000000110 8/4 00c 000h to 00dfffh 006000h to 006fffh sa7 0000000111 8/4 00e 000h to 00ffffh 007000h to 007fffh sa8 0000001xxx 64/320 10000h to 01ffffh 008000h to 00ffffh sa9 0000010xxx 64/320 20000h to 02ffffh 010000h to 017fffh sa10 0000011xxx 64/320 30000h to 03ffffh 018000h to 01ffffh sa11 0000100xxx 64/320 40000h to 04ffffh 020000h to 027fffh sa12 0000101xxx 64/320 50000h to 05ffffh 028000h to 02ffffh sa13 0000110xxx 64/320 60000h to 06ffffh 030000h to 037fffh sa14 0000111xxx 64/320 70000h to 07ffffh 038000h to 03ffffh sa15 0001000xxx 64/320 80000h to 08ffffh 040000h to 047fffh sa16 0001001xxx 64/320 90000h to 09ffffh 048000h to 04ffffh sa17 0001010xxx 64/320a0000h to 0affffh0 50000h to 057fffh sa18 0001011xxx 64/320b0000h to 0bffffh05 8000h to 06ffffh sa19 0001100xxx 64/320c0 000h to 0cffffh 060000h to 067fffh sa20 0001101xxx 64/320d0 000h to 0dffffh 068000h to 06ffffh sa21 0001110xxx 64/320e0000h to 0effffh0 70000h to 077fffh sa22 0001111xxx 64/320f0000h to 0fffffh07 8000h to 07ffffh
mbm29dl640e 80/90/12 15 table 6.2 sector address tables (bank b) (continued) bank sec- tor sector address sector size (kbytes / kwords) ( 8) address range ( 16) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa23 0010000xxx 64/321 00000h to 10ffffh 080000h to 087fffh sa24 0010001xxx 64/321 10000h to 11ffffh 088000h to 08ffffh sa25 0010010xxx 64/321 20000h to 12ffffh 090000h to 097fffh sa26 0010011xxx 64/321 30000h to 13ffffh 098000h to 09ffffh sa27 0010100xxx 64/321 40000h to 14ffffh 0a0000h to 0a7fffh sa28 0010101xxx 64/321 50000h to 15ffffh 0a8000h to 0affffh sa29 0010110xxx 64/321 60000h to 16ffffh 0b0000h to 0b7fffh sa30 0010111xxx 64/321 70000h to 17ffffh 0b8000h to 0bffffh sa31 0011000xxx 64/321 80000h to 18ffffh 0c0000h to 0c7fffh sa32 0011001xxx 64/321 90000h to 19ffffh 0c8000h to 0cffffh sa33 0011010xxx 64/321a0000h to 1affffh0d0000h to 0d7fffh sa34 0011011xxx 64/321b0000h to 1bffffh0d8000h to 0dffffh sa35 0011100xxx 64/321c0 000h to 1cffffh 0e0000h to 0e7fffh sa36 0011101xxx 64/321d0 000h to 1dffffh 0e8000h to 0effffh sa37 0011110xxx 64/321e0000h to 1effffh0f0000h to 0f7fffh sa38 0011111xxx 64/321f0000h to 1fffffh0f 8000h to 0fffffh sa39 0100000xxx 64/322 00000h to 20ffffh 100000h to 107fffh sa40 0100001xxx 64/322 10000h to 21ffffh 108000h to 10ffffh sa41 0100010xxx 64/322 20000h to 22ffffh 110000h to 117fffh sa42 0100011xxx 64/322 30000h to 23ffffh 118000h to 11ffffh sa43 0100100xxx 64/322 40000h to 24ffffh 120000h to 127fffh sa44 0100101xxx 64/322 50000h to 25ffffh 128000h to 12ffffh sa45 0100110xxx 64/322 60000h to 26ffffh 130000h to 137fffh sa46 0100111xxx 64/322 70000h to 27ffffh 138000h to 13ffffh sa47 0101000xxx 64/322 80000h to 28ffffh 140000h to 147fffh sa48 0101001xxx 64/322 90000h to 29ffffh 148000h to 14ffffh sa49 0101010xxx 64/322a0000h to 2affffh1 50000h to 157fffh sa50 0101011xxx 64/322b0000h to 2bffffh15 8000h to 15ffffh sa51 0101100xxx 64/322c0 000h to 2cffffh 160000h to 167fffh sa52 0101101xxx 64/322d0 000h to 2dffffh 168000h to 16ffffh sa53 0101110xxx 64/322e0000h to 2effffh1 70000h to 177fffh
mbm29dl640e 80/90/12 16 (continued) note : the address range is a 21 : a -1 if in byte mode (byte = v il ) . the address range is a 21 : a 0 if in word mode (byte = v ih ) . bank sec- tor sector address sector size (kbytes / kwords) ( 8) address range ( 16) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa54 0101111xxx 64/322f0000h to 2fffffh17 8000h to 17ffffh sa55 0110000xxx 64/323 00000h to 30ffffh 180000h to 187fffh sa56 0110001xxx 64/323 10000h to 31ffffh 188000h to 18ffffh sa57 0110010xxx 64/323 20000h to 32ffffh 190000h to 197fffh sa58 0110011xxx 64/323 30000h to 33ffffh 198000h to 19ffffh sa59 0110100xxx 64/323 40000h to 34ffffh 1a0000h to 1a7fffh sa60 0110101xxx 64/323 50000h to 35ffffh 1a8000h to 1affffh sa61 0110110xxx 64/323 60000h to 36ffffh 1b0000h to 1b7fffh sa62 0110111xxx 64/323 70000h to 37ffffh 1b8000h to 1bffffh sa63 0111000xxx 64/323 80000h to 38ffffh 1c0000h to 1c7fffh sa64 0111001xxx 64/323 90000h to 39ffffh 1c8000h to 1cffffh sa65 0111010xxx 64/323a0000h to 3affffh1d0000h to 1d7fffh sa66 0111011xxx 64/323b0000h to 3bffffh1d8000h to 1dffffh sa67 0111100xxx 64/323c0 000h to 3cffffh 1e0000h to 1e7fffh sa68 0111101xxx 64/323d0 000h to 3dffffh 1e8000h to 1effffh sa69 0111110xxx 64/323e0000h to 3effffh1f0000h to 1f7fffh sa70 0111111xxx 64/323f0000h to 3fffffh1f 8000h to 1fffffh
mbm29dl640e 80/90/12 17 table 6.3 sector address tables (bank c) (continued) bank sec- tor sector address sector size (kbytes / kwords) ( 8) address range ( 16) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa71 1000000xxx 64/324 00000h to 40ffffh 200000h to 207fffh sa72 1000001xxx 64/324 10000h to 41ffffh 208000h to 20ffffh sa73 1000010xxx 64/324 20000h to 42ffffh 210000h to 217fffh sa74 1000011xxx 64/324 30000h to 43ffffh 218000h to 21ffffh sa75 1000100xxx 64/324 40000h to 44ffffh 220000h to 227fffh sa76 1000101xxx 64/324 50000h to 45ffffh 228000h to 22ffffh sa77 1000110xxx 64/324 60000h to 46ffffh 230000h to 237fffh sa78 1000111xxx 64/324 70000h to 47ffffh 238000h to 23ffffh sa79 1001000xxx 64/324 80000h to 48ffffh 240000h to 247fffh sa80 1001001xxx 64/324 90000h to 49ffffh 248000h to 24ffffh sa81 1001010xxx 64/324a0000h to 4affffh2 50000h to 257fffh sa82 1001011xxx 64/324b0000h to 4bffffh25 8000h to 25ffffh sa83 1001100xxx 64/324c0 000h to 4cffffh 260000h to 267fffh sa84 1001101xxx 64/324d0 000h to 4dffffh 268000h to 26ffffh sa85 1001110xxx 64/324e0000h to 4effffh2 70000h to 277fffh sa86 1001111xxx 64/324f0000h to 4fffffh27 8000h to 27ffffh sa87 1010000xxx 64/325 00000h to 50ffffh 280000h to 287fffh sa88 1010001xxx 64/325 10000h to 51ffffh 288000h to 28ffffh sa89 1010010xxx 64/325 20000h to 52ffffh 290000h to 297fffh sa90 1010011xxx 64/325 30000h to 53ffffh 298000h to 29ffffh sa91 1010100xxx 64/325 40000h to 54ffffh 2a0000h to 2a7fffh sa92 1010101xxx 64/325 50000h to 55ffffh 2a8000h to 2affffh sa93 1010110xxx 64/325 60000h to 56ffffh 2b0000h to 2b7fffh sa94 1010111xxx 64/325 70000h to 57ffffh 2b8000h to 2bffffh sa95 1011000xxx 64/325 80000h to 58ffffh 2c0000h to 2c7fffh sa96 1011001xxx 64/325 90000h to 59ffffh 2c8000h to 2cffffh sa97 1011010xxx 64/325a0000h to 5affffh2d0000h to 2d7fffh sa98 1011011xxx 64/325b0000h to 5bffffh2d8000h to 2dffffh sa99 1011100xxx 64/325c0 000h to 5cffffh 2e0000h to 2ee7ffh sa1001011101xxx 64/325d0 000h to 5dffffh 2e8000h to 2effffh sa1011011110xxx 64/325e0000h to 5effffh2f0000h to 2f7fffh sa1021011111xxx 64/325f0000h to 5fffffh2f 8000h to 2fffffh
mbm29dl640e 80/90/12 18 (continued) note : the address range is a 21 : a -1 if in byte mode (byte = v il ) . the address range is a 21 : a 0 if in word mode (byte = v ih ) . bank sec- tor sector address sector size (kbytes / kwords) ( 8) address range ( 16) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa1031100000xxx 64/326 00000h to 60ffffh 300000h to 307fffh sa1041100001xxx 64/326 10000h to 61ffffh 308000h to 30ffffh sa1051100010xxx 64/326 20000h to 62ffffh 310000h to 317fffh sa1061100011xxx 64/326 30000h to 63ffffh 318000h to 31ffffh sa1071100100xxx 64/326 40000h to 64ffffh 320000h to 327fffh sa1081100101xxx 64/326 50000h to 65ffffh 328000h to 32ffffh sa1091100110xxx 64/326 60000h to 66ffffh 330000h to 337fffh sa1101100111xxx 64/326 70000h to 67ffffh 338000h to 33ffffh sa1111101000xxx 64/326 80000h to 68ffffh 340000h to 347fffh sa1121101001xxx 64/326 90000h to 69ffffh 348000h to 34ffffh sa1131101010xxx 64/326a0000h to 6affffh3 50000h to 357fffh sa1141101011xxx 64/326b0000h to 6bffffh35 8000h to 35ffffh sa1151101100xxx 64/326c0 000h to 6cffffh 360000h to 367fffh sa1161101101xxx 64/326d0 000h to 6dffffh 368000h to 36ffffh sa1171101110xxx 64/326e0000h to 6effffh3 70000h to 377fffh sa1181101111xxx 64/326f0000h to 6fffffh37 8000h to 37ffffh
mbm29dl640e 80/90/12 19 table 6.4 sector address tables (bank d) note : the address range is a 21 : a -1 if in byte mode (byte = v il ) . the address range is a 21 : a 0 if in word mode (byte = v ih ) . bank sec- tor sector address sector size (kbytes / kwords) ( 8) address range ( 16) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa1191110000xxx 64/32700 000h to 70ffffh 380000h to 387fffh sa1201110001xxx 64/32710 000h to 71ffffh 388000h to 38ffffh sa1211110010xxx 64/32720 000h to 72ffffh 390000h to 397fffh sa1221110011xxx 64/32730 000h to 73ffffh 398000h to 39ffffh sa1231110100xxx 64/32740 000h to 74ffffh 3a0000h to 3a7fffh sa1241110101xxx 64/32750 000h to 75ffffh 3a8000h to 3affffh sa1251110110xxx 64/32760 000h to 76ffffh 3b0000h to 3b7fffh sa1261110111xxx 64/32770 000h to 77ffffh 3b8000h to 3bffffh sa1271111000xxx 64/32780 000h to 78ffffh 3c0000h to 3c7fffh sa1281111001xxx 64/32790 000h to 79ffffh 3c8000h to 3cffffh sa1291111010xxx 64/327a0 000h to 7affffh 3d0000h to 3d7fffh sa1301111011xxx 64/327b0 000h to 7bffffh 3d8000h to 3dffffh sa1311111100xxx 64/327c0000h to 7cffffh3e0000h to 3e7fffh sa1321111101xxx 64/327d0000h to 7dffffh3e 8000h to 3effffh sa1331111110xxx 64/327e0 000h to 7effffh 3f0000h to 3f7fffh sa1341111111000 8/4 7f0 000h to 7f1fffh 3f8000h to 3f8fffh sa1351111111001 8/4 7f2 000h to 7f3fffh 3f9000h to 3f9fffh sa1361111111010 8/4 7f4 000h to 7f5fffh 3fa000h to 3fafffh sa1371111111011 8/4 7f6 000h to 7f7fffh 3fb000h to 3fbfffh sa1381111111100 8/4 7f8 000h to 7f9fffh 3fc000h to 3fcfffh sa1391111111101 8/4 7fa 000h to 7fbfffh 3fd000h to 3fdfffh sa1401111111110 8/4 7fc0 00h to 7fdfffh 3fe000h to 3fefffh sa1411111111111 8/4 7fe000h to 7fffffh3ff000h to 3fffffh
mbm29dl640e 80/90/12 20 table 7 sector group address table (continued) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0000000000 sa0 sga1 0000000001 sa1 sga2 0000000010 sa2 sga3 0000000011 sa3 sga4 0000000100 sa4 sga5 0000000101 sa5 sga6 0000000110 sa6 sga7 0000000111 sa7 sga8 00000 00 xxx sa8 to sa10 01 10 sga9 00001 xxxxxsa11 to sa14 sga10 00010 xxxxxsa15 to sa18 sga11 00011 xxxxxsa19 to sa22 sga12 00100 xxxxxsa23 to sa26 sga13 00101 xxxxxsa27 to sa30 sga14 00110 xxxxxsa31 to sa34 sga15 00111 xxxxxsa35 to sa38 sga16 01000 xxxxxsa39 to sa42 sga17 01001 xxxxxsa43 to sa46 sga18 01010 xxxxxsa47 to sa50 sga19 01011 xxxxxsa51 to sa54 sga20 01100 xxxxxsa55 to sa58 sga21 01101 xxxxxsa59 to sa62 sga22 01110 xxxxxsa63 to sa66 sga23 01111 xxxxxsa67 to sa70
mbm29dl640e 80/90/12 21 (continued) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga24 10000 xxxxxsa71 to sa74 sga25 10001 xxxxxsa75 to sa78 sga26 10010 xxxxxsa79 to sa82 sga27 10011 xxxxxsa83 to sa86 sga28 10000 xxxxxsa87 to sa90 sga29 10101 xxxxxsa91 to sa94 sga30 10110 xxxxxsa95 to sa98 sga31 10111 xxxxxsa99 to sa102 sga32 11000 xxxxxsa103 to sa106 sga33 11001 xxxxxsa107 to sa110 sga34 11010 xxxxxsa111 to sa114 sga35 11011 xxxxxsa115 to sa118 sga36 11100 xxxxxsa119 to sa122 sga37 11101 xxxxxsa123 to sa126 sga38 11110 xxxxxsa127 to sa130 sga39 11111 00 x x x sa131 to sa133 01 10 sga40 1111111000 sa134 sga41 1111111001 sa135 sga42 1111111010 sa136 sga43 1111111011 sa137 sga44 1111111100 sa138 sga45 1111111101 sa139 sga46 1111111110 sa140 sga47 1111111111 sa141
mbm29dl640e 80/90/12 22 description a 6 to a 0 dq 15 to dq 0 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 2h : amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min. (write/erase) d7-4 : 1 v, d3-0 : 100 mv 1bh 0027h v cc max. (write/erase) d7-4 : 1 v, d3-0 : 100 mv 1ch 0036h v pp min. voltage 1dh 0000h v pp max. voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min. size buffer write 2 n m s 20h 0000h typical timeout per individual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max. timeout for byte/word write 2 n times typical 23h 0005h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0017h flash device interface description : 8 / 16 28h 29h 0002h 0000h max. number of bytes in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0003h erase block region 1 information bit 0 to 15: y = number of sectors bit 16 to 31: z = size (z 256 bytes) 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information bit 0 to 15: y = number of sectors bit 16 to 31: z = size (z 256 bytes) 31h 32h 33h 34h 007dh 0000h 0000h 0001h erase block region 3 information bit 0 to 15: y = number of sectors bit 16 to 31: z = size (z 256 bytes) 35h 36h 37h 38h 0007h 0000h 0020h 0000h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0033h address sensitive unlock 0h = required 1h = not required 45h 0000h erase suspend 0h = not supported 1h = to read only 2h = to read & write 46h 0002h sector protection 0h = not supported x = number of sectors per group 47h 0001h sector temporary unprotection 00h = not supported 01h = supported 48h 0001h sector protection algorithm 49h 0004h simultaneous operation 00h = not supported x = total number of sectors in all banks except bank 1 4ah 0077h burst mode type 00h = not supported 4bh 0000h page mode type 00h = not supported 4ch 0000h acc (acceleration) supply minimum 00h = not supported, d7-4 : 1 v, d3-0 : 100 mv 4dh 0085h acc (acceleration) supply maximum 00h = not supported, d7-4 : 1 v, d3-0 : 100 mv 4eh 0095h boot type 4fh 0001h program suspend 00h = not supported 01h = supported 50h 0001h bank organization 00h = if data at 4ah is zero. x = number of banks 57h 0004h bank a region information x = number of sectors in bank a 58h 0017h bank b region information x = number of sectors in bank b 59h 0030h bank c region information x = number of sectors in bank c 5ah 0030h bank d region information x = number of sectors in bank d 5bh 0017h description a 6 to a 0 dq 15 to dq 0 table 8 common flash memory interface code
mbm29dl640e 80/90/12 23 n n n n functional description simultaneous operation the device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . the bank can be selected by bank address (a 21 , a 20 , a 19 ) with zero latency. the device consists of the following four banks : bank a : 8 8 kb and 15 64 kb; bank b : 48 64 kb; bank c : 48 64 kb; bank d : 8 8 kb and 15 64 kb. the device can execute simultaneous operations between bank 1, a bank chosen from among the four banks, and bank 2, a bank consisting of the three remaining banks. (see table 9.) this is what we call a flexbank, for example, the rest of banks b, c and d to let the system read while bank a is in the process of program (or erase) operation. however, the different types of operations for the three banks are impossible, e.g. bank a writing, bank b erasing, and bank c reading out. with this flexbank, as described in table 10, the system gets to select from four combinations of data volume for bank 1 and bank 2, which works well to meet the system requirement. the simultaneous operation cannot execute multi-function mode in the same bank. table 11 shows the possible combinations for simultaneous operation. (refer to figure 11 bank-to-bank read/write timing diagram.) table 9 flexbank tm architecture table 10 example of virtual banks combination note : when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for example, suppose that erasing is taking place at both bank a and bank b, neither bank a nor bank b is read out (they would output the sequence flag once they were selected.) meanwhile the system would get to read from either bank c or bank d. bank splits bank 1 bank 2 volume combination volume combination 1 8 mbit bank a 56 mbit remainder (bank b, c, d) 2 24 mbit bank b 40 mbit remainder (bank a, c, d) 3 24 mbit bank c 40 mbit remainder (bank a, b, d) 4 8 mbit bank d 56 mbit remainder (bank a, b, c) bank splits bank 1 bank 2 volume combination sector size volume combination sector size 18 mbit bank a 8 8 kbyte/4 kword + 15 64 kbyte/32 kword 56 mbit bank b + bank c + bank d 8 8 kbyte/4 kword + 111 64 kbyte/32 kword 216 mbit bank a + bank d 16 8 kbyte/4 kword + 30 64 kbyte/32 kword 48 mbit bank b + bank c 96 64 kbyte/32 kword 3 24 mbit bank b 48 64 kbyte/32 kword 40 mbit bank a + bank c + bank d 16 8 kbyte/4 kword + 78 64 kbyte/32 kword 432 mbit bank a + bank b 8 8 kbyte/4 kword + 63 64 kbyte/32 kword 32 mbit bank c + bank d 8 8 kbyte/4 kword + 63 64 kbyte/32 kword
mbm29dl640e 80/90/12 24 table 11 simultaneous operation * : by writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. note: bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks, bank a, bank b, bankc and bank d. bank address (ba) meant to specify each of the banks. read mode the device has two control functions which are required in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins. address access time (t acc ) is equal to delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc -t oe time) . when reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h or l standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins, and the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset input held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even if ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l) . under this condition the current consumed is less than 5 m a max. once the reset pin is set high, the device requires t rh as a wake-up time for output to be valid for read access. during standby mode, the output is in the high impedance state, regardless of oe input. case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mbm29dl640e 80/90/12 25 automatic sleep mode automatic sleep mode works to restrain power consumption during read-out of device data. it can be useful in applications such as handy terminal, which requires low power consumption. to activate this mode, the device automatically switches itself to low power mode when the device addresses remain stable during access time of 150 ns. it is not necessary to control ce , we and oe in this mode. in this mode the current consumed is typically 1 m a (cmos level) . during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are continuously read out. when the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. output disable with the oe input at a logic high level (v ih ) , output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.it is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id on address pin a 9 . three identifier bytes may then be sequenced from the device outputs by toggling addresses. all addresses are dont cares except a 6 , a 3 , a 2 , a 1 and a 0 (a -1 ) . (see tables 2 and 3.) the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 4. (refer to autoselect command section.) in the command autoselect mode, the bank addresses ba; (a 21 , a 20 , a 19 ) must point to a specific bank during the third write bus cycle of the autoselect command. then the autoselect data will be read from that bank while array data can be read from the other bank. in word mode, a read cycle from address 00h returns the manufacturers code (fujitsu = 04h) . a read cycle at address 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at addresses of 0eh and 0fh. notice that the above applies to word mode; the addresses and codes differ from those of byte mode. (refer to table 5.1 and 5.2. ) in the case of applying v id on a 9 , since both bank 1 and bank 2 enter autoselect mode, simultanous operation cannot be executed. write device erasure and programming are accomplished via the command register. the contents of the register serve as input to the internal state machine. the state machine output dictates the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later, while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters.
mbm29dl640e 80/90/12 26 sector group protection the device features hardware sector group protection. this feature will disable both program and erase opera- tions in any combination of forty eight sector groups of memory. (see table 7) . the users side can use the sector group protection using programming equipment. the device is shipped with all sector groups that are unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il and a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih . the sector group addresses (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) should be set to the sector to be protected. tables 6.1 to 6.4 define the sector address for each of the one hundred forty-two (142) individual sectors, and table 7 defines the sector group address for each of the forty eight (48) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see figures 18 and 26 for sector group protection waveforms and algorithms. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sectors. in this mode, the lower order addresses, except for a 0 , a 1 , a 2 , a 3 and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires applying to v il on byte mode. whether the sector group is protected in the system can be determined by writing an autoselect command. performing a read operation at the address location (ba) xx02h, where the higher order addresses (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group address, will produce a logical 1 at dq 0 for a protected sector group. note that the bank addresses (a 21 , a 20 , a 19 ) must be pointing to a specific bank during the third write bus cycle of the autoselect command. then the autoselect data can be read from that bank while array data can still be read from the other bank. to read autoselect data from the other bank, it must be reset to read mode and then write the autoselect command to the other bank. see tables 5.1 and 5.2 for autoselect codes. temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the device in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ) . during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad- dresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to figures 19 and 27. extended sector group protection in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables protection of the sector group by forcing v id on reset pin and writes a command sequence. unlike conventional procedures, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition the operation is initiated by writing the set-up command (60h) in the command register. then the sector group addresses pins (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (setting v il for the other addresses pins is recommended) , and an extended sector group protection command (60h) should be written. a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set a command (40h) should be written. following the command write, a logical 1 at device output dq 0 will produce a protected sector in the read operation. if the output is logical 0, write the extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . (refer to figures 20 and 28.)
mbm29dl640e 80/90/12 27 reset hardware reset the device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high the device requires an additional t rh before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see figure 14 for the timing diagram. refer to temporary sector group unprotection for additional functionality. boot block sector protection the write protection function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the two outermost 8 kbytes on both ends of boot sectors independently of whether those sectors are protected or unprotected using the method described in sector protection/unprotection. (mbm29dl640e : sa0, sa1, sa140, and sa141) if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 8 kbyte on both ends of boot sectors were last set to be protected or unprotected. sector protection or unprotection for these four sectors depends on whether they were last protected or unprotected using the method described in sector protection/unprotection. accelerated program operation the device offers accelerated program operation which enables programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60 % . this function is primarily intended to allow high speed programming, so caution is needed as the sector group will temporarily be unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device is automatically set to fast mode. therefore, the present sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see figure 21.
mbm29dl640e 80/90/12 28 n n n n command definitions device operations are selected by writing specific address and data sequences into the command register. some commands require bank address (ba) input. when command sequences are input into a bank reading, the commands have priority over the reading. table 4 shows the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress. moreover, read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. micro- processor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case a command sequence is not required in order to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to ac read char- acteristics and timing diagram for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. therefore, manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a higher voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated first by writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. the higher order address (a 21 , a 20 , a 19 ) required for reading out the manufacture and device codes demands the bank address (ba) set at the third write cycle. following the command write, in word mode, a read cycle from address (ba) 00h returns the manufacturers code (fujitsu = 04h) . and a read cycle at address (ba) 01h outputs device code. when 227eh was output, this indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh. notice that the above applies to word mode. the addresses and codes differ from those of byte mode. (refer to table 5.1 and 5.2. ) the sector state (protection or unprotection) will be informed by address (ba) 02h for 16 ( (ba) 04h for 8) . scanning the sector group addresses (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verifying sector group protection on the protected sector. (see tables 2 and 3.) the manufacture and device codes can be read from the selected bank. to read the manufacture and device codes and sector protection status from a non-selected bank, it is necessary to write the read/reset command sequence into the register. autoselect command should then be written into the bank to be read. if the software (program code) for autoselect command is stored in the flash memory, the device and manu- facture codes should be read from the other bank, which does not contain the software. to terminate the operation, it is necessary to write the read/reset command sequence into the register. to execute the autoselect command during the operation, read/reset command sequence must be written before the autoselect command.
mbm29dl640e 80/90/12 29 byte/word programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later, and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) starts programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated pro- gram pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling) , dq 6 (toggle bit) or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see table 12, hardware sequence flags). therefore, the device requires that a valid address to the device be supplied by the system in this particular instance. hence, data polling must be performed at the memory location which is being programmed. if hardware reset occurs during the programming operation, the data being written is not guaranteed. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert from 0s to 1s. figure 22 illustrates the embedded program tm algorithm using typical command strings and bus operations. program suspend/resume the program suspend command allows the system to interrupt a program operation so that data can be read from any address. writing the program suspend command (b0h) during the embedded program operation immediately suspends the programming. the program suspend command may also be issued during a pro- gramming operation while an erase is suspended. the bank addresses of sector being programmed should be set when writing the program suspend command. when the program suspend command is written during a programming process, the device halts the program operation within 1 m s and updates the status bits. after the program operation has been suspended, the system can read data from any address. the data at program-suspended address is not valid. normal read timing and command definitions apply. after the program resume command (30h) is written, the device reverts to programming. the bank addresses of sectors being suspended should be set when writing the program resume command. the system can determine the status of the program operation using the dq 7 or dq 6 status bits, just as in the standard program operation. see write operation status for more information. the system may also write the autoselect command sequence when the device in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the program resume command (address bits are bank address) to exit from the program suspend mode and continue the programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device has resumed programming. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence, the device will automatically program and verify the entire memory for an all-
mbm29dl640e 80/90/12 30 zero data pattern prior to electrical erase (preprogram function) . the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence, and terminates when the data on dq 7 is 1 (see write operation status section), at which time the device returns to the read mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) figure 23 illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we , whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we , whichever happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation begins. multiple sectors may be erased concurrently by writing the six bus cycle operations on table 4. this sequence is followed by writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow . otherwise, that command will not be accepted and erasure will not start. it is recommended that processor interrupts be disabled during this time to guarantee such a condition. the interrupts can reoccur after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we , whichever happens first, will initiate the execution of the sector erase command (s) . if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window, the timer is reset (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer). resetting the device once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete (refer to write operation status section for sector erase timer operation). loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 141) . sector erase does not require the user to program the device before erase. the device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (preprogram function) . when erasing a sector, the rest remain unaffected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) or ry/by . the sector erase begins after the t tow time-out from the rising edge of ce or we , whichever happens first, for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section), at which time the device returns to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time = [sector erase time + sector program time (preprogramming) ] number of sector erase in case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed. figure 23 illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt sector erase operation and then reads data from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. writing the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation.
mbm29dl640e 80/90/12 31 writing the erase resume command (30h) resumes the erase operation. the bank address of sector being erased or erase-suspended should be set when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device takes a maximum of t spd to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin will be at hi-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle (see the section on dq 2 ). after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, it is the same as programming in the regular program mode, except that the data must be programmed to sectors that are not erase-suspended. reading successively from the erase-suspended sector while the device is in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ), which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode the device has a fast mode function. it dispenses with the initial two unclock cycles required in the standard program command sequence by writing the fast mode command into the command register. in this mode, the required bus cycle for programming consists of two bus cycles instead of four in standard program command. do not write erase command in this mode. the read operation is also executed after exiting from the fast mode. to exit from this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address (see figure 29) .the v cc active current is required even if ce = v ih during fast mode. (2) fast programming during fast mode, programming can be executed with two bus cycle operation. the embedded program algo- rithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd) (see figure 29) . (3) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and the host system software interro- gation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent and forward-and backward-compatible soft- ware support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. the bank address should be set when writing this command. then the device information can be read from the bank, and data from the memory cell can be read from the another bank. the higher order address (a 21 , a 20 , a 19 ) required for reading out the cfi codes requires that the bank address (ba) be set at the write cycle. following the command write, a read cycle from specific address retrieves device information. please note that output data of upper byte (dq 15 to dq 8 ) is 0 in word mode (16 bit) read. refer to cfi code table (table 12) . to terminate operation, it is necessary to write the read/reset command sequence into the register.
mbm29dl640e 80/90/12 32 hidden rom (hi-rom) region the hi-rom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hi-rom region is protected, any further modifi- cation of that region becomes impossible. this ensures the security of the esn once the product is shipped to the field. the hi-rom region is 256 bytes in length and is stored at the same address of the outermost 8 kbyte boot sector in bank a. the device occupies the address of the byte mode 000000h to 0000ffh (word mode 000000h to 00007fh) . after the system has written the enter hi-rom command sequence, the system may read the hi- rom region by using the addresses normally occupied by the boot sector (particular area of sa0) . that is, the device sends all commands that would normally be sent to the boot sector (particular area of sa0) to the hi- rom region. this mode of operation continues until the system issues the exit hi-rom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sector. when reading the hi-rom region, either change addresses or change ce pin from h to l. the same procedure should be taken (changing addresses or ce pin from h to l) after the system issues the exit hi-rom command sequence to read actual memory cell data. hidden rom (hi-rom) entry command the device has a hidden rom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. programming is allowed in this area until it is protected. however, once it gets protected, it is impossible to unprotect. therefore, extreme caution is required. the hidden rom area is 256 bytes. this area is normally the outermost 8 kbyte boot block area in bank a. therefore, write the hidden rom entry command sequence to enter the hidden rom area. it is called hidden rom mode when the hidden rom area appears. sectors other than the boot block area sa0 can be read during hidden rom mode. read/program of the hidden rom area is possible during hidden rom mode. write the hidden rom reset command sequence to exit the hidden rom mode. the bank address of the hidden rom should be set on the third cycle of this reset command sequence. in hidden rom mode, the simultaneous operation cannot be executed multi-function mode between the hidden rom area and the bank a. hidden rom (hi-rom) program command to program the data to the hidden rom area, write the hidden rom program command sequence during hidden rom mode. this command is the same as the usual program command, except that it needs to write the command during hidden rom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data pooling, dq 6 toggle bit and ry/by pin. you should pay attention to the address to be programmed. if an address not in the hidden rom area is selected, the previous data will be deleted. hidden rom (hi-rom) protect command there are two methods to protect the hidden rom area. one is to write the sector group protect setup command (60h) , set the sector address in the hidden rom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the hidden rom mode. the same command sequence may be used because it is the same as the extension sector group protect in the past, except that it is in the hidden rom mode and does not apply high voltage to the reset pin. please refer to function explanation extended sector group protection for details of extension sector group protect setting. the other method is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hidden rom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) , and apply the write pulse during the hidden rom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) and the sector address in the hidden rom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 will appear on dq 0 if it is not protected. apply write pulse again. the same command sequence could be used for the above
mbm29dl640e 80/90/12 33 method because other than the hidden rom mode, it is the same as the sector group protect previously mentioned. refer to function explanation secor group protection for details of the sector group protect setting. take note that other sector groups will be affected if an address other than those for the hidden rom area is selected for the sector group address, so please be careful. pay close attention that once it is protected, protection cannot be cancelled. write operation status detailed in table 12 are all the status flags which can determine the status of the bank for the current mode operation. the read operation from the bank which doesnt operate embedded algorithm returns data of memory cells. these bits offer a method for determining whether an embedded algorithm is properly completed. the information on dq 2 is address-sensitive. this means that if an address from an erasing sector is consecutively read, the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows users to determine which sectors are in erase and which are not. the status flag is not output from banks (non-busy banks) which do not execute embedded algorithms. for example, a bank (busy bank) is executing an embedded algorithm. when the read sequence is [1] < busy bank > , [2] < non-busy bank > , [3] < busy bank > , the dq 6 toggles in the case of [1] and [3]. in case of [2], the data of memory cells are output. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in [1] and [3]. in the erase suspend read mode, dq 2 is toggled in [1] and [3]. in case of [2], the data of memory cell is output. table 12 hardware sequence flags *1: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2: reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. notes: 1. dq 0 and dq 1 are reserve pins for future use. 2. dq 4 is limited to fujitsu internal use. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle * 1 program suspended mode program suspend read (program suspended sector) data data data data data program suspend read (non-program suspended sec- tor) data data data data data erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1 * 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29dl640e 80/90/12 34 dq 7 data polling the device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm, an attempt to read device will produce a 1 on dq 7 . the flowchart for data polling (dq 7 ) is shown in figure 24. for programming, the data polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. data polling must be performed at sector addresses of sectors being erased, not pro- tected sectors. otherwise the status may become invalid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the device data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that device is driving status information on dq 7 at one instant, and then that bytes valid data at the next instant. depending on when the system samples the dq 7 output, it may read the status or valid data. even if device has completed the embedded algorithm operation and dq 7 has a valid data, data outputs on dq 0 to dq 6 may still be invalid. the valid data on dq 0 to dq 7 will be read on successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see table 12.) see figure 9 for the data polling timing specifications and diagrams. dq 6 toggle bit i the device also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the busy bank will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequences. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequences. the toggle bit i is active during the sector time out. in programming, if the sector being written is protected, the toggle bit will toggle for about 1 m s and then stop toggling with data unchanged. in erase, the device will erase all selected sectors except for protected ones. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data kept remained. either ce or oe toggling will cause dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erased or is erase-suspended. when a bank is actively erased (that is, the embedded erase algorithm is in progress) , dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during erase-suspend-program cause dq 6 to toggle. to operate toggle bit function properly, ce or oe must be high when bank address is changed. see figure 10 for the toggle bit i timing specifications and diagrams.
mbm29dl640e 80/90/12 35 dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions dq 5 will produce 1. this is a failure condition indicating that the program or erase cycle was not successfully completed. data polling is only operating function of the device under this condition. the ce circuit will partially power down device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in tables 2 and 3. the dq 5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads valid data on dq 7 bit and dq 6 never stop toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset device with the command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence, sector erase time-out begins. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates that a valid erase command has been written, dq 3 may be used to determine whether the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun. if dq 3 is low (0) , the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see table 12 : hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also table 13 and figure 12. furthermore dq 2 can also be used to determine which sector is being erased. at the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed. reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle.
mbm29dl640e 80/90/12 36 however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to figure 25.) table 13 toggle bit status note : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from the non- erase suspend sector address will indicate logic 1 at the dq 2 bit. ry/by ready/busy the device provides a ry/by open-drain output pin as a way to indicate to the host system that embedded algorithms are either in progress or have been completed. if output is low, the device is busy with either a program or erase operation. if output is high, the device is ready to accept any read/write or erase operation. if the device is placed in an erase suspend mode, ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during reset pulse. refer to figures 13 and 14 for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . byte/word configuration byte pin selects byte (8-bit) mode or word (16-bit) mode for the device. when this pin is driven high, the device operates in word (16-bit) mode. data is read and programmed at dq 15 to dq 0 . when this pin is driven low, the device operates in byte (8-bit) mode. in this mode, the dq 15 /a -1 pin becomes the lowest address bit, and dq 14 to dq 8 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. refer to figures 15, 16 and 17 for the timing diagram. data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power-up, the device automatically resets the internal state machine in read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle (note) erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1 (note)
mbm29dl640e 80/90/12 37 low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min.) . if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min.) . if the embedded erase algorithm is interrupted, the intervened erasing sector (s) is (are) not valid. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29dl640e 80/90/12 38 n n n n absolute maximum ratings notes : 1. minimum dc voltage on input or i/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe and reset pins is - 0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe and reset pins is + 13.0 v which may overshoot to + 14.0 v for periods of up to 20 ns. 3. minimum dc input voltage on wp /acc pin is - 0.5 v. during voltage transitions, wp /acc pin may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is + 10.5 v which may overshoot to + 12.0 v for periods of up to 20 ns when vcc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating ranges warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. operating ranges define those limits between which the proper device function is guaranteed. parameter symbol rating unit min. max. storage temperature tstg - 55 + 125 c ambient temperature with power applied ta - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , and reset (note 1) v in , v out - 0.5 v cc + 0.5 v power supply voltage (note 1) v cc - 0.5 + 4.0 v a 9 , oe , and reset (note 2) v in - 0.5 + 13.0 v wp /acc (note 3) v acc - 0.5 + 10.5 v parameter symbol part no. ranges unit min. max. ambient temperature ta mbm29dl640e 80 - 20 + 70 c mbm29dl640e 90/12 - 40 + 85 c power supply voltage v cc mbm29dl640e 80 + 3.0 + 3.6 v mbm29dl640e 90/12 + 2.7 + 3.6 v
mbm29dl640e 80/90/12 39 n n n n maximum overshoot/undershoot + 0.6 v - 0.5 v 20 ns - 2.0 v 20 ns 20 ns figure 1 maximum undershoot waveform v cc + 0.5 v + 2.0 v v cc + 2.0 v 20 ns 20 ns 20 ns figure 2 maximum overshoot waveform 1 + 13.0 v v cc + 0.5 v + 14.0 v 20 ns 20 ns 20 ns figure 3 maximum overshoot waveform 2 note : this waveform is applied for a9, oe and reset .
mbm29dl640e 80/90/12 40 n n n n electrical characteristics 1. dc characteristics *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4: applicable for only v cc . *5: embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol conditions value unit min. typ. max. input leakage current i li v in = v ss to v cc , v cc = v cc max. - 1.0 ?+ 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max. - 1.0 ?+ 1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max., a 9 , oe , reset = 12.5 v ??+ 35 m a wp /acc accelerated program current i lia v cc = v cc max. wp /acc = v acc max. ?? 20 ma v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 5 mhz byte ?? 16 ma word ?? 18 ce = v il , oe = v ih , f = 1 mhz byte ?? 7 ma word ?? 7 v cc active current * 2 i cc2 ce = v il , oe = v ih ?? 40 ma v cc current (standby) i cc3 v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v wp /acc = v cc 0.3 v ? 15 m a v cc current (standby, reset) i cc4 v cc = v cc max., reset = v ss 0.3 v ? 15 m a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max., ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v ? 15 m a v cc active current * 5 (read-while-program) i cc6 ce = v il , oe = v ih byte ?? 56 ma word ?? 58 v cc active current * 5 (read-while-erase) i cc7 ce = v il , oe = v ih byte ?? 56 ma word ?? 58 v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih ?? 40 ma input low level v il ?- 0.5 ? 0.6 v input high level v ih ? 2.0 ? v cc + 0.3 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id ? 11.5 12 12.5 v voltage for wp /acc sector protection/unprotection and program acceleration * 4 v acc ? 8.5 9.0 9.5 v output low voltage level v ol i ol = 100 m a, v cc = v cc min. ?? 0.45 v output high voltage level v oh1 i oh = - 2.0 ma, v cc = v cc min. 2.4 ?? v v oh2 i oh = - 100 m a v cc - 0.4 ?? v low v cc lock-out voltage v lko ? 2.3 2.4 2.5 v
mbm29dl640e 80/90/12 41 2. ac characteristics ? read only operations characteristics note : test conditions : output load : 1 ttl gate and 30 pf (mbm29dl640e-80) 1 ttl gate and 100 pf (mbm29dl640e-90/120) input rise and fall times : 5 ns input pulse levels : 0.0 v to 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v parameter symbol condition value (note) unit 80 90 12 jedec standard min. max. min. max. min. max. read cycle time t avav t rc ? 80 ? 90 ? 120 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 80 ? 90 ? 120 ns chip enable to output delay t elqv t ce oe = v il ? 80 ? 90 ? 120 ns output enable to output delay t glqv t oe ?? 30 ? 35 ? 50 ns chip enable to output high-z t ehqz t df ?? 25 ? 30 ? 30 ns output enable to output high-z t ghqz t df ?? 25 ? 30 ? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ? 0 ? 00 ? ns reset pin low to read mode ? t ready ?? 20 ? 20 ? 20 m s ce to byte switching low or high ? t elfl t elfh ?? 5 ? 5 ? 5ns c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w figure 4 test conditions
mbm29dl640e 80/90/12 42 ? write/erase/program operations (continued) parameter symbol value unit 80 90 12 jedec standard min. typ. max. min. typ. max. min. typ. max. write cycle time t avav t wc 80 ?? 90 ?? 120 ?? ns address setup time t avwl t as 0 ?? 0 ?? 0 ?? ns address setup time to oe low during toggle bit polling ? t aso 12 ?? 15 ?? 15 ?? ns address hold time t wlax t ah 45 ?? 45 ?? 50 ?? ns address hold time from ce or oe high during toggle bit polling ? t aht 0 ?? 0 ?? 0 ?? ns data setup time t dvwh t ds 30 ?? 35 ?? 50 ?? ns data hold time t whdx t dh 0 ?? 0 ?? 0 ?? ns output enable hold time read ? t oeh 0 ?? 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? 10 ?? ns ce high during toggle bit polling ? t ceph 20 ?? 20 ?? 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? 20 ?? 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 35 ?? 50 ?? ns ce pulse width t eleh t cp 35 ?? 35 ?? 50 ?? ns write pulse width high t whwl t wph 25 ?? 30 ?? 30 ?? ns ce pulse width high t ehel t cph 25 ?? 30 ?? 30 ?? ns programming operation byte t whwh1 t whwh1 ? 8 ?? 8 ?? 8 ?m s word ? 16 ?? 16 ?? 16 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ?? 1 ? s v cc setup time ? t vcs 50 ?? 50 ?? 50 ??m s rise time to v id * 2 ? t vidr 500 ?? 500 ?? 500 ?? ns rise time to v acc * 3 ? t vaccr 500 ?? 500 ?? 500 ?? ns voltage transition time * 2 ? t vlht 4 ?? 4 ?? 4 ??m s write pulse width * 2 ? t wpp 100 ?? 100 ?? 100 ??m s
mbm29dl640e 80/90/12 43 (continued) *1: this does not include preprogramming time. *2: this timing is for sector group protection operation. *3: this timing is for accelerated program operation. parameter symbol value unit 80 90 12 jedec standard min. typ. max. min. typ. max. min. typ. max. oe setup time to we active * 2 ? t oesp 4 ?? 4 ?? 4 ??m s ce setup time to we active * 2 ? t csp 4 ?? 4 ?? 4 ??m s recover time from ry/by ? t rb 0 ?? 0 ?? 0 ?? ns reset pulse width ? t rp 500 ?? 500 ?? 500 ?? ns reset high level period before read ? t rh 200 ?? 200 ?? 200 ?? ns byte switching low to output high-z ? t flqz ?? 30 ?? 30 ?? 40 ns byte switching high to output active ? t fhqv ?? 80 ?? 90 ?? 120 ns program/erase valid to ry/by delay ? t busy ?? 90 ?? 90 ?? 90 ns delay time from embedded output enable ? t eoe ?? 80 ?? 90 ?? 120 ns erase time-out time ? t tow 50 ?? 50 ? 50 ??m s erase suspend transition time ? t spd ?? 20 ?? 20 ?? 20 m s
mbm29dl640e 80/90/12 44 n n n n erase and programming performance n n n n tsop (i) pin capacitance note : test conditions ta = 25 c, f = 1.0 mhz n n n n fbga pin capacitance note : test conditions ta = 25 c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time ? 110s excludes programming time prior to erasure word programming time ? 16 360 m s excludes system-level overhead byte programming time ? 8 300 m s chip programming time ?? 200 s excludes system-level overhead program/erase cycle 100,000 ?? cycle ? parameter symbol condition value unit typ. max. input capacitance c in v in = 067.5pf output capacitance c out v out = 08.512pf control pin capacitance c in2 v in = 0811pf wp /acc pin capacitance c in3 v in = 0911pf parameter symbol condition value unit typ. max. input capacitance c in v in = 0tbdtbdpf output capacitance c out v out = 0tbdtbdpf control pin capacitance c in2 v in = 0tbdtbdpf wp /acc pin capacitance c in3 v in = 0tbdtbdpf
mbm29dl640e 80/90/12 45 n n n n timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will change from h to l will change from l to h changing, state unknown center line is high- impedance "off" state address address stable high-z high-z ce oe we outputs outputs valid t rc t acc t oe t df t ce t oh t oeh figure 5.1 read operation timing diagram
mbm29dl640e 80/90/12 46 address ce reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh figure 5.2 hardware reset/read operation timing diagram
mbm29dl640e 80/90/12 47 address data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t df t oh t oe t cs t ch notes : 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) figure 6 alternate we controlled program operation timing diagram
mbm29dl640e 80/90/12 48 address data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh figure 7 alternate ce controlled program operation timing diagram notes : 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29dl640e 80/90/12 49 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h 30h for sector erase figure 8 chip/sector erase operation timing diagram * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase. note : these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29dl640e 80/90/12 50 figure 9 data polling during embedded algorithm operation timing diagram * : dq 7 = valid data (the device has completed the embedded operation) . t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data *
mbm29dl640e 80/90/12 51 t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph figure 10 ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling (the device has completed the embedded operation).
mbm29dl640e 80/90/12 52 ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) figure 11 bank-to-bank read/write timing diagram note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2 figure 12 dq 2 vs. dq 6 note : dq 2 is read from the erase-suspended sector. enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 we toggle dq 2 and dq 6 with oe
mbm29dl640e 80/90/12 53 figure 13 ry/by timing diagram during program/erase operation timing diagram ce ry/by we the rising edge of the last we signal t busy entire programming or erase operations figure 14 reset , ry/by timing diagram t rp t rb t ready ry/by we reset
mbm29dl640e 80/90/12 54 figure 15 timing diagram for word mode configuration t ce t fhqv t elfh a -1 data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) dq 15 ce byte dq 14 to dq 0 dq 15 /a -1 figure 16 timing diagram for byte mode configuration t elfl t acc t flqz a -1 data output (dq 14 to dq 0 ) data output (dq 7 to dq 0 ) dq 15 ce byte dq 14 to dq 0 dq 15 /a -1 figure 17 byte timing diagram for write operations t as t ah ce or we byte input valid falling edge of the last write signal
mbm29dl640e 80/90/12 55 t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 21 , a 20 , a 19 a 18 , a 17 , a 16 a 15 , a 14 , a 13 a 12 a 6 , a 3 , a 2 , a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data spax 01h spay figure 18 sector group protection timing diagram spax : sector group address to be protected spay : next sector group address to be protected note : a- 1 is v il on byte mode.
mbm29dl640e 80/90/12 56 figure 19 temporary sector group unprotection timing diagram unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce reset
mbm29dl640e 80/90/12 57 figure 20 extended sector group protection timing diagram spax : sector group address to be protected spay : next sector group address to be protected time-out : time-out window = 250 m s (min.) v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out spax spax spay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 3 , a 2 , a 0 a 1
mbm29dl640e 80/90/12 58 figure 21 accelerated program timing diagram v ih wp/acc vcc ce we ry/by t vlht program or erase command sequence t vlht t vcs t vaccr vacc t vlht acceleration period
mbm29dl640e 80/90/12 59 n n n n flow chart figure 22 embedded program tm algorithm note : the sequence is applied for 16 mode. the addresses differ from 8 mode. embedded algorithm 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in program
mbm29dl640e 80/90/12 60 figure 23 embedded erase tm algorithm note : the sequence is applied for 16 mode. the addresses differ from 8 mode. embedded algorithm 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional.
mbm29dl640e 80/90/12 61 figure 24 data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes
mbm29dl640e 80/90/12 62 figure 25 toggle bit algorithm *1 : read toggle bit twice to determine whether or not it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. toggle bit = toggle? dq 5 = 1? toggle bit = toggle? read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va read dq 7 to dq 0 twice addr. = va start no no no yes yes yes *1 *1, 2 program/erase operation not complete.write reset command program/erase operation complete va = bank address being executed embedded algorithm.
mbm29dl640e 80/90/12 63 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group? increment plscnt read from sector group addr. = spa, a 1 = v ih a 6 = a 3 = a 2 = a 0 = v il setup sector group addr. a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () () * figure 26 sector group protection algorithm * : a -1 is v il in byte mode.
mbm29dl640e 80/90/12 64 start perform erase or program operations reset = v id *1 reset = v ih temporary sector group unprotection completed *2 figure 27 temporary sector group unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are reprotected.
mbm29dl640e 80/90/12 65 start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector protection completed protect other sector group? increment plscnt read from sector group address (addr. = spa, a 0 = v il , a 1 = v ih , a 6 = v il ) remove v id from reset write reset command time out 250 m s reset = v id wait to 4 m s no yes setup next sector address device is operating in temporary sector group unprotection mode to protect sector group write 60h to sector address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to verify sector group protection write 40h to sector address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to setup sector group protection write xxxh/60h extended sector group protection entry? figure 28 extended sector group protection algorithm
mbm29dl640e 80/90/12 66 555h/aah 555h/20h xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address? increment address verify data? data polling start no no yes yes set fast mode in fast program reset fast mode (ba) figure 29 embedded programming algorithm for fast mode notes: the sequence is applied for 16 mode. the addresses differ from 8 mode. fast mode algorithm
mbm29dl640e 80/90/12 67 n n n n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of : mbm29dl640 e 80 tn device number/description mbm29dl640 64 mega-bit (8 m 8-bit or 4 m 16-bit) cmos flash memory 3.0 v-only read, program, and erase pa c k a g e t y p e tn = 48-pin thin small outline package (tsop) standard pinout tr = 48-pin thin small outline package (tsop) reverse pinout pbt = 63-ball fine pitch ball grid array package (fbga) speed option see product selector guide device revision valid combinations mbm29dl640e 80 90 12 tn tr pbt valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
mbm29dl640e 80/90/12 68 n n n n package dimensions 48-pin plastic tsop (i) (fpt-48p-m19) * resin protrusion. (each side : 0.15 (.006) max) dimensions in mm (inches) c 1996 fujitsu limited f48029s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.400.20 (.724.008) 20.000.20 (.787.008) 19.000.20 (.748.008) 0.10(.004) 0.500.10 (.020.004) 0.150.05 (.006.002) 11.50ref (.460) 0.50(.0197) typ 0.200.10 (.008.004) 0.05(0.02)min .043 .002 +.004 0.05 +0.10 1.10 m 0.10(.004) stand off 1 24 25 48 lead no. * * 12.000.20 (.472.008) (mounting height)
mbm29dl640e 80/90/12 69 48-pin plastic tsop (i) (fpt-48p-m20) * resin protrusion. (each side : 0.15 (.006) max) dimensions in mm (inches) c 1996 fujitsu limited f48030s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.400.20 (.724.008) 20.000.20 (.787.008) 19.000.20 (.748.008) 0.10(.004) 0.500.10 (.020.004) 0.150.10 (.006.002) 11.50(.460)ref 0.50(.0197) typ 0.200.10 (.008.004) 0.05(0.02)min .043 .002 +.004 0.05 +0.10 1.10 m 0.10(.004) stand off 1 24 25 48 lead no. * * 12.000.20(.472.008) (mounting height)
mbm29dl640e 80/90/12 70 63-ball plastic fbga (bga-63p-m02) dimensions in mm (inches) c 1999 fujitsu limited b63002s-1c-1 11.00?.10(.433?004) .041 ?004 +.006 ?.10 +0.15 1.05 (mounting height) 1 2 3 4 5 6 7 8 a b c d e f g h 0.80(.031)typ (5.60(.220)) (5.60(.220)) index ball m 0.08(.003) 0.10(.004) index area 10.00?.10 (.394?004) (7.20(.283)) j k (63-0.18?002) 63-0.45?.05 ml (8.80(.346)) (4.00(.157)) 0.38?.10 (.015?004) (stand off)
mbm29dl640e 80/90/12 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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